EPSL: Executable Protocol Specification Language

Motivation. The verification of bus protocols, i.e., of communication protocols between hardware devices as in the case of the well-known PCI bus, is a central problem in hardware verification. Although bus protocol design and verification become increasingly important due to the integration of diverse components in IP Core-based designs, even standard bus protocols are usually specified in English which makes specifications often ambiguous, contradictory and certainly non-executable. Traditional hardware verification languages are usually not well-suited for protocol specification because they are based on existing concrete designs (or abstractions thereof) instead of specifications, and their execution model therefore focuses on single-cycle transitions. With protocols, the specification is naturally represented by constraints on signals which may connect relatively distant time points. Another problem of transition-system based approaches is that naive composition of participants in the protocol may cover up important protocol inconsistencies due to synchronization faults or write conflicts among non-cooperative participants. On the other hand, it is important that the specification language is executable, i.e., that a machine model can be computed from the specification.