Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS

Four divide-by-3 injection-locked frequency dividers (ILFDs) are fabricated in 40-nm CMOS technology. A second-harmonic peaking technique is used to enhance the locking range. The distributed inductor technique is used to enhance the operation frequency and the locking range. The locking range and design considerations of the proposed ILFDs are discussed. The largest measured locking range among four ILFDs is 236.6~245.2 GHz. The highest operation frequency is over 280 GHz. These ILFDs consume 2.97~3.96 mW from a supply of 1.1 V excluding output buffers.

[1]  Ulrich Langmann,et al.  A 90GHz 65nm CMOS Injection-Locked Frequency Divider , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Bo-Yu Lin,et al.  Analysis and Design of D-Band Injection-Locked Frequency Dividers , 2011, IEEE Journal of Solid-State Circuits.

[3]  Jeng-Han Tsai,et al.  Design and Analysis of a 77.3% Locking-Range Divide-by-4 Frequency Divider , 2011, IEEE Transactions on Microwave Theory and Techniques.

[4]  I-Ting Lee,et al.  A 3.6 mW 125.7–131.9 GHz Divide-by-4 Injection-Locked Frequency Divider in 90 nm CMOS , 2012, IEEE Microwave and Wireless Components Letters.

[5]  Frederick Warren Grover,et al.  Inductance Calculations: Working Formulas and Tables , 1981 .

[6]  M. Tiebout,et al.  A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider , 2004, IEEE Journal of Solid-State Circuits.

[7]  Shen-Iuan Liu,et al.  A 198.9GHz-to-201.0GHz injection-locked frequency divider in 65nm CMOS , 2010, 2010 Symposium on VLSI Circuits.

[8]  I-Ting Lee,et al.  Current-reused divide-by-3 injection-locked frequency divider in 65 nm CMOS , 2011 .

[9]  Lin Zhang,et al.  A 16-to-18GHz 0.18-m Epi-CMOS Divide-by-3 Injection-Locked Frequency Divider , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[10]  I-Ting Lee,et al.  3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[11]  Hong-Yeh Chang,et al.  Design and Analysis of a $W$-band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique , 2012, IEEE Transactions on Microwave Theory and Techniques.

[12]  258.16-259.95 GHz injection-locked frequency divider , 2010 .

[13]  Zhiwei Xu,et al.  CMOS Prescaler(s) With Maximum 208-GHz Dividing Speed and 37-GHz Time-Interleaved Dual-Injection Locking Range , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  F. Svelto,et al.  Analysis and design of injection-locked LC dividers for quadrature generation , 2004, IEEE Journal of Solid-State Circuits.

[15]  Payam Heydari,et al.  Theoretical Analysis of Novel Multi-Order LC Oscillators , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[16]  Huei Wang,et al.  A 66–72 GHz divide-by-3 injection-locked frequency divider in 0.13-μm CMOS technology , 2007, 2007 IEEE Asian Solid-State Circuits Conference.

[17]  Shen-Iuan Liu,et al.  A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[18]  Y.-J.E. Chen,et al.  A 60-GHz 0.13-$\mu{\hbox{m}}$ CMOS Divide-by-Three Frequency Divider , 2008, IEEE Transactions on Microwave Theory and Techniques.

[19]  Yu-Ling Lin,et al.  A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS , 2010, IEEE Custom Integrated Circuits Conference 2010.