A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology
暂无分享,去创建一个
[1] Poki Chen,et al. A CMOS pulse-shrinking delay element for time interval measurement , 2000 .
[2] M.Z. Straayer,et al. A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping , 2009, IEEE Journal of Solid-State Circuits.
[3] P. Dudek,et al. A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line , 2000, IEEE Journal of Solid-State Circuits.
[4] Poras T. Balsara,et al. 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[5] K. Muhammad,et al. All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.
[6] Kwyro Lee,et al. A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme , 1997, IEEE J. Solid State Circuits.
[7] A.A. Abidi,et al. A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.
[8] I. Nissinen,et al. A CMOS time-to-digital converter based on a ring oscillator for a laser radar , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).