Two-stage placement for VLSI analogue layout designs

The shortcomings of conventional separate placement and global routing becomes more prevalent for analogue integrated circuits that often involve complex constraints. The paper presents a novel two-stage placement technique to solve the analogue macro-cell placement problem. The entire placement procedure is divided into global placement and detailed placement. During the global placement, a hybrid genetic placement approach using a half-perimeter net-length estimator is employed. It performs a rough and quick search to locate the region of the optimum. In the detailed placement, a very fast simulated re-annealing placement approach and a minimum-Steiner-tree-based global routing are performed simultaneously. In this way, the optimum can be found by searching a relatively small region. The experiments show this promising algorithm, which provides the satisfactory results comparable to expert manual placements, can help generate higher quality layouts than conventional approaches.