Exact Minimization of and-EXOR Expressions of Practical Benchmark Functions

We propose faster-computing methods for the minimization algorithm of AND–EXOR expressions, or exclusive-or sum-of-products expressions (ESOPs), and obtain the exact minimum ESOPs of benchmark functions. These methods improve the search procedure for ESOPs, which is the most time-consuming part of the original algorithm. For faster computation, the search space for ESOPs is reduced by checking the upper and lower bounds on the size of ESOPs. Experimental results to demonstrate the effectiveness of these methods are presented. The exact minimum ESOPs of many practical benchmark functions have been revealed by this improved algorithm.

[1]  Tsutomu Sasao,et al.  A simplification method for AND-EXOR expressions for multiple-output functions , 1996, Systems and Computers in Japan.

[2]  George K. Papakonstantinou,et al.  Exact ESCT minimization for functions of up to six input variables , 2008, Integr..

[3]  Hirayama Takashi,et al.  Double Fixed-Polarity Reed-Muller Expressions:A New Class of AND-EXOR Expressions for Compact and Testable Realization , 2001 .

[4]  Kensuke Shimizu,et al.  Lower Bounds on Size of Periodic Functions in Exclusive-OR Sum-of-Products Expressions (Special Section on the 6th Karuizawa Workshop on Circuits and Systems) , 1994 .

[5]  Takashi Hirayama,et al.  Efficient search methods for obtaining exact minimum AND-EXOR expressions , 2006, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06).

[6]  George K. Papakonstantinou,et al.  Multiple-Value Exclusive-Or Sum-Of-Products Minimization Algorithms , 2004 .

[7]  SUDHAKAR M. REDDY,et al.  Easily Testable Realizations ror Logic Functions , 1972, IEEE Transactions on Computers.

[8]  Tsutomu Sasao.  EXMIN: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued input two-valued output functions , 1990, Proceedings of the Twentieth International Symposium on Multiple-Valued Logic.

[9]  M. Perkowski,et al.  An exact algorithm to minimize mixed-radix exclusive sums of products for incompletely specified Boolean functions , 1990, IEEE International Symposium on Circuits and Systems.

[10]  Douglas V. Hall,et al.  A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits , 2000, IEEE Trans. Computers.

[11]  Kensuke Shimizu,et al.  Exor Decomposition with Common Variables and its Application to Multiple-Output Networks , 1999, J. Circuits Syst. Comput..

[12]  Takashi Hirayama,et al.  A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions , 1996, Systems and Computers in Japan.

[13]  Guowu Yang,et al.  Majority-based reversible logic gates , 2005, Theor. Comput. Sci..

[14]  George K. Papakonstantinou,et al.  Exact Minimization Of Esop Expressions With Less Than Eight Product Terms , 2004, J. Circuits Syst. Comput..

[15]  Santanu Chattopadhyay,et al.  KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Tsutomu Sasao,et al.  On the complexity of mod-2l sum PLA's , 1990 .

[17]  Tsutomu Sasao,et al.  Representations of Logic Functions Using EXOR Operators , 1996 .

[18]  Shimon Even,et al.  On Minimal Modulo 2 Sums of Products for Switching Functions , 1966, SWAT.

[19]  Tsutomu Sasao.  Easily Testable Realizations for Generalized Reed-Muller Expressions , 1997, IEEE Trans. Computers.

[20]  A. Mishchenko,et al.  Fast Heuristic Minimization of Exclusive-Sums-of-Products , 2001 .

[21]  G. Bioul.  Minimization of ring-sum expansion of Boolean functions , 1973 .

[22]  Marek A. Perkowski,et al.  Minimization of exclusive sum-of-products expressions for multiple-valued input, incompletely specified functions , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Yahiko Kambayashi,et al.  Transformation rules for designing CNOT-based quantum circuits , 2002, DAC '02.

[24]  Kaushik Roy,et al.  An XOR-Based Decomposition Diagram and Its Application in Synthesis of AND/XOR Networks (Special Section on VLSI Design and CAD Algorithms) , 1997 .

[25]  Fabrizio Luccio,et al.  On a New Boolean Function with Applications , 1999, IEEE Trans. Computers.

[26]  Harold Fleisher,et al.  A Computer Algorithm for Minimizing Reed-Muller Canonical Forms , 1987, IEEE Transactions on Computers.

[27]  George K. Papakonstantinou,et al.  A fast and efficient heuristic ESOP minimization algorithm , 2004, GLSVLSI '04.

[28]  Tsutomu Sasao,et al.  Minimization of AND-EXOR Expressions Using Rewrite Rules , 1993, IEEE Trans. Computers.

[29]  Tsutomu Sasao,et al.  Minimization of AND-OR-EXOR Three-Level Networks with AND Gate Sharing (Special Issue on Synthesis and Verification of Hardware Design) , 1997 .

[30]  Marek A. Perkowski,et al.  A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms , 1988, DAC '88.

[31]  Kensuke Shimizu,et al.  Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions , 1999 .

[32]  Tsutomu Sasao.  Multiple-valued logic and optimization of programmable logic arrays , 1988, Computer.

[33]  Toru Sato,et al.  A faster algorithm of minimizing AND-EXOR expressions , 2002, Asia-Pacific Conference on Circuits and Systems.