Theorems for Fault Collapsing in Combinational Circuits

This paper gives a mathematical approach to fault collapsing based on the stuck-at fault model for combinational circuits. The mathematical structure we work within is a Boolean ring of Boolean functions of several variables. The goal of fault collapsing for a given circuit is to reduce the number of stuck-at faults to be considered in test generation and fault diagnosis. For this purpose we need rules that let us eliminate faults from the considered fault set. In this paper some earlier known rules are proved in the new context, and several new rules are presented and proved. The most important of the new theorems deal with the relationship between stuck-at faults on a fanout stem and the branches. The concept of monotony of Boolean functions appears to be important in most of these new rules.

[1]  A. Lloy,et al.  Advanced fault collapsing (logic circuits testing) , 1992 .

[2]  Antonio Lioy,et al.  Looking for Functional Fault Equivalence , 1991, 1991, Proceedings. International Test Conference.

[3]  Samuel C. Lee.  Modern Switching Theory and Digital Design , 1978 .

[4]  Vishwani D. Agrawal,et al.  A new algorithm for global fault collapsing into equivalence and dominance sets , 2002, Proceedings. International Test Conference.

[5]  Hideo Fujiwara,et al.  Logic Testing and Design for Testability , 1985 .

[6]  Jwue Chen,et al.  CIRCUIT EXAMPLE TO DEMONSTRATE THAT FAN-OUT STEMS OF PRIMARY INPUTS MUST BE CHECKPOINTS , 1989 .

[7]  Antonio Lioy.  On the Equivalence of Fanout-Point Faults , 1993, IEEE Trans. Computers.

[8]  Irith Pomeranz,et al.  Fault equivalence identification in combinational circuits using implication and evaluation techniques , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Jwu E. Chen,et al.  Checkpoints in irredundant two-level combinational circuits , 1991, J. Electron. Test..

[10]  Vamsi Boppana,et al.  Diagnostic fault equivalence identification using redundancy information and structural analysis , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[11]  Wen-Zen Shen,et al.  Fanout fault analysis for digital logic circuits , 1995, Proceedings of the Fourth Asian Test Symposium.

[12]  Larry L. Dornhoff,et al.  Applied Modern Algebra , 1978 .

[13]  Rabindra K. Roy,et al.  Dynamic redundancy identification in automatic test generation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Vishwani D. Agrawal,et al.  Fault collapsing via functional dominance , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[15]  Jean-Pierre Deschamps,et al.  Discrete and switching functions , 1978 .

[16]  Thomas C. Bartee,et al.  Modern Applied Algebra , 1999 .

[17]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.