Programming Tools for Reconfigurable Processors

The capability to tailor the processor instruction set architecture (ISA) around the computational requirements of a given application is proposed today as the most appealing way to match performance with very short time-to-market, accomplishing the reduction of non-recurring engineering (NRE) costs. From Mask-Time Configurable Processors (MTCPs) to Run-Time Reconfigurable Processors (RTRPs), the ISA customization is performed “moving” kernels of initial code from software to hardware, thus introducing a design space exploration problem involving skills in both software and hardware design. Since adaptive processors appear as the natural extension of Digital Signal Processors (DSPs), programming tools for customizable processors need to be as similar as possible to standard software development environments, in order to enable the adaptive computing to the wide audience of DSP programmers. While fast design-space explorations can be performed using high-level description languages, programmers proficient in hardware design can further improve the performance through “structural” descriptions involving, for example, the direct utilization of macro-operators or the possibility of balancing critical paths through register insertion. The widespread knowledge of the ANSI C among developers suggests its usage as main entry language for both configurable and reconfigurable architectures, thus introducing the problem of translating C codes (or C dialects) into some kind of hardware description, be it HDL in case of MTCPs or bit-stream for RTRPs. In this context, Data-Flow Graphs (DFGs) can be efficiently used to close the gap between hardware and software design, thus representing the most natural bridge between the hardware and software descriptions. Furthermore, standard ANSI C can be used by the programmer for the management of the application control flow on the processor core, embedding custom-designed instructions in

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