A 64-MHz∼640-MHz 64-phase clock generator

This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18μm CMOS process with an area of 500×620um2. The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps.

[1]  Wei Hwang,et al.  A 1.7mW all digital phase-locked loop with new gain generator and low power DCO , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[2]  Bang-Sup Song,et al.  A CMOS 1×-16× speed DVD write channel IC , 2006 .

[3]  K. Tomioka,et al.  A CMOS 1/spl times/-16/spl times/ speed DVD write channel IC , 2006, IEEE Journal of Solid-State Circuits.

[4]  Ching-Che Chung,et al.  A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications , 2006 .

[5]  J.A. Tierno,et al.  A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI , 2008, IEEE Journal of Solid-State Circuits.

[6]  U. Karthaus,et al.  Write pulse Generator for 16x DVD recording with symmetric CMOS inverter ring oscillator , 2005, IEEE Journal of Solid-State Circuits.

[7]  Jin-Young Kim,et al.  An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme , 2006, IEEE Journal of Solid-State Circuits.

[8]  T. Morie,et al.  A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[9]  Kee-Won Kwon,et al.  An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[10]  T. Morie,et al.  A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System , 2008, IEEE Journal of Solid-State Circuits.