Compact Modeling and Analysis of Through-Si-Via-Induced Electrical Noise Coupling in Three-Dimensional ICs

Through-silicon vias (TSVs) in 3-D integrated circuits (ICs), which are used for connecting different active layers, introduce an important source of coupling noise arising from electrical coupling between TSVs and the active regions. This paper, for the first time, presents compact models based on a fully analytical approach for the electrical coupling from a TSV to the active regions for a comprehensive set of 3-D IC substrate technologies including those with and without the high-conductivity buried layer in dual-well bulk CMOS technology in the presence of VDD/VSS rails. The models can be used during design validation of emerging 3-D ICs. The compact physical models are verified against full-wave electromagnetic (EM) simulations. A comparative analysis of the magnitude of the EM coupling noise for different 3-D technology scenarios, including both dual-well bulk CMOS and partially depleted silicon-on-insulator, is also presented. The compact models presented for dual-well bulk CMOS are subsequently employed for estimating the stay-away radius (safe distance) from the center of the TSVs to the active regions to minimize the impact of such coupling noise. In order to highlight the significance of the TSV to active-region EM coupling noise, a comparison is also made with the white noise in the active region and the flicker noise from the interface between the TSV oxide and silicon.

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