Object-oriented domain specific compilers for programming FPGAs
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[1] William J. Dally,et al. A bandwidth-efficient architecture for media processing , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.
[2] Juan Manuel Moreno,et al. A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[3] Jean-Marc Delosme,et al. Highly concurrent computing structures for matrix arithmetic and signal processing , 1982, Computer.
[4] Herman Schmit,et al. PCI-PipeRench and the SWORDAPI: a system for stream-based reconfigurable computing , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).
[5] Marco Platzner,et al. Acceleration of Satisfiability Algorithms by Reconfigurable Hardware , 1998, FPL.
[6] Carl Ebeling,et al. Mapping applications to the RaPiD configurable architecture , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[7] Oskar Mencer,et al. Application of Reconfigurable CORDIC Architectures , 1998, Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284).
[8] Michael J. Flynn,et al. Hardware software tri-design of encryption for mobile communication units , 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).
[9] Jean Vuillemin,et al. Programmable Active Memories: A Performance Assessment , 1992, Heinz Nixdorf Symposium.
[10] Steve McKeever,et al. Pebble: A Language for Parametrised and Reconfigurable Hardware Design , 1998, FPL.
[11] Michael J. Flynn,et al. PAM-Blox: high performance FPGA design for adaptive computing , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).
[12] Xuejia Lai,et al. Markov Ciphers and Differential Cryptanalysis , 1991, EUROCRYPT.
[13] Makoto Yokoo,et al. Solving Satisfiability Problems on FPGAs , 1996, FPL.
[14] M. Flynn,et al. Rational arithmetic units in computer systems , 2000 .
[15] H. T. Kung. Why systolic architectures? , 1982, Computer.
[16] Karl S. Hemmert,et al. A CAD suite for high-performance FPGA design , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).
[17] Sharad Malik,et al. Accelerating Boolean satisfiability with configurable hardware , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).
[18] Patrick Schaumont,et al. Hardware reuse at the behavioral level , 1999, DAC '99.
[19] Ephraim Feig,et al. New scaled DCT algorithms for fused multiply/add architectures , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.
[20] Giovanni De Micheli,et al. Synthesis and Optimization of Digital Circuits , 1994 .
[21] Joao Marques-Silva,et al. GRASP-A new search algorithm for satisfiability , 1996, Proceedings of International Conference on Computer Aided Design.