论文信息 - L/sup 2/RFM-local layout realistic faults mapping scheme for analogue integrated circuits

L/sup 2/RFM-local layout realistic faults mapping scheme for analogue integrated circuits

A new fault modelling scheme for analogue ICs called Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout. Defects are assumed and their electrical failure modes are evaluated. It turned out that some faults at schematic level are unrealistic, new types of fault emerge and the distribution of faults changes. For a CMOS operational amplifier the number of faults dropped from 45 to 27.

M. J. Ohletz

[1] Yves Crouzet,et al. Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.

[2] J.W. Bandler,et al. Fault diagnosis of analog circuits , 1985, Proceedings of the IEEE.

[3] Linda S. Milor,et al. Detection of catastrophic faults in analog integrated circuits , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4] C.H. Stapper,et al. Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[5] John Paul Shen,et al. Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[6] João Paulo Teixeira,et al. Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[7] C. Morandi,et al. Failure modes and mechanisms for VLSI ICs - a review , 1985 .

[8] E. A. Amerasekera,et al. Failure Mechanisms in Semiconductor Devices , 1987 .

[9] Wojciech Maly,et al. Physically realistic fault models for analog CMOS neural networks , 1991 .

[10] Pierre Duhamel,et al. Automatic test generation techniques for analog circuits and systems: A review , 1979 .