Time-predictable chip-multiprocessor design
暂无分享,去创建一个
[1] Martin Schoeberl,et al. Design and implementation of an efficient stack machine , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.
[2] Peter Marwedel,et al. Overlay techniques for scratchpad memories in low power embedded processors , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[3] Benedikt Huber,et al. Worst‐case execution time analysis for a Java processor , 2010, Softw. Pract. Exp..
[4] Martin Schoeberl,et al. A Java processor architecture for embedded real-time systems , 2008, J. Syst. Archit..
[5] Jack Whitham,et al. Real-time processor architectures for worst case execution time reduction , 2008 .
[6] Benedikt Huber,et al. Towards Time-Predictable Data Caches for Chip-Multiprocessors , 2009, SEUS.
[7] Reinhard Wilhelm,et al. The influence of processor architecture on the design and the results of WCET tools , 2003, Proceedings of the IEEE.
[8] Benedikt Huber,et al. WCET driven design space exploration of an object cache , 2010, JTRES '10.
[9] Colin Whitby-Strevens. The transputer , 1985, ISCA 1985.
[10] Martin Schoeberl,et al. A Time Predictable Instruction Cache for a Java Processor , 2004, OTM Workshops.
[11] Andy J. Wellings,et al. Thread-Local Scope Caching for Real-time Java , 2009, 2009 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing.
[12] Martin Schoeberl,et al. A real-time Java chip-multiprocessor , 2010, TECS.
[13] Martin Schoeberl,et al. Time-predictable Cache Organization , 2009, 2009 Software Technologies for Future Dependable Distributed Systems.
[14] Martin Schoeberl. Application Experiences with a Real-Time Java Processor , 2008 .
[15] Martin Schoeberl,et al. Is Chip-Multiprocessing the End of Real-Time Scheduling? , 2009, WCET.
[16] James Gosling,et al. The Real-Time Specification for Java , 2000, Computer.
[17] Stephen A. Edwards,et al. A disruptive computer design idea: Architectures with repeatable timing , 2009, 2009 IEEE International Conference on Computer Design.
[18] Sascha Uhrig,et al. How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT , 2010, ARCS.
[19] R. Wilhelm,et al. Predictability Considerations in the Design of Multi-Core Embedded Systems ∗ , 2010 .
[20] Martin Schoeberl,et al. Time-Predictable Computer Architecture , 2009, EURASIP J. Embed. Syst..
[21] Neil C. Audsley,et al. Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures , 2008, 2008 IEEE Real-Time and Embedded Technology and Applications Symposium.
[22] C. A. R. Hoare,et al. Communicating sequential processes , 1978, CACM.
[23] S. Uhrig,et al. Toward a processor core for real-time capable autonomic systems , 2005, Proceedings of the Fifth IEEE International Symposium on Signal Processing and Information Technology, 2005..
[24] Fridtjof Siebert. JEOPARD -- Java Environment for Parallel Real-Time Development , 2009, 2009 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing.
[25] Per Stenström,et al. Timing anomalies in dynamically scheduled microprocessors , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).
[26] Neil C. Audsley,et al. Time-Predictable Out-of-Order Execution for Hard Real-Time Systems , 2010, IEEE Transactions on Computers.
[27] Martin Schoeberl,et al. NoC-based CSP support for a Java chip multiprocessor , 2010, NORCHIP 2010.
[28] Stephen A. Edwards,et al. The Case for the Precision Timed (PRET) Machine , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[29] Edward A. Lee,et al. A PRET architecture supporting concurrent programs with composable timing properties , 2010, 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers.
[30] Stephen A. Edwards,et al. Predictable programming on a precision timed architecture , 2008, CASES '08.
[31] Heung Seok Chae,et al. An adaptive load balancing management technique for RFID middleware systems , 2010 .
[32] Luca Benini,et al. Polynomial-time algorithm for on-chip scratchpad memory partitioning , 2003, CASES '03.
[33] Neil C. Audsley,et al. Implementing time-predictable load and store operations , 2009, EMSOFT '09.