A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator

To overcome the minimum-delay constraint of latch based error detection and correction (EDAC) techniques, we propose a technique of using pulse latch and transition detector (TD). This method is also advantageous in no need of error recovery by time-borrowing characteristics of the latch. To detect timing violations and minimize the area overhead, we design a quick-response 15-transistor transition detector cover a wide-voltage range from near-threshold voltage (NTV) to Super-Vth. Test chips are fabricated in 28nm CMOS process. Silicon measurements demonstrate that the whole design has achieved up to 64.3% energy saving with 180mV additional voltage scaling, compared to the conventional worst-case design at the expense of 4.3% area overhead.