NASICs: A nanoscale fabric for nanoscale microprocessors

The rapid progress of manufacturing nanoscale devices is pushing researchers to explore appropriate nanoscale computing architectures for high density beyond the physical limitations of conventional lithography. However, manufacturing and layout constraints, as well as high defect/fault rates expected in nanoscale fabrics, could make most device density lost when integrated into computing systems. Therefore, a nanoscale architecture that can deal with those constraints and tolerate defects/faults at expected rates, while still retaining the density advantage, is highly desirable. In this paper, we describe a novel nanoscale architecture based on semiconductor nanowires: NASICs (nanoscale application specific ICs). NASIC is a tile-based fabric built on 2-D nanowire grids and NW FETs. WISP-0 (wire streaming processor) is a processor design built on NASIC fabric where NASIC design principles and optimizations are applied. Built-in fault tolerance techniques are applied on NASICs designs to tolerate defects/faults on-the-fly. Evaluations show that compared with the equivalent CMOS design with 18 nm process (the most advanced technology expected in 2018), WISP-0 with combined built-in redundancy could be still 2~3X denser. Its yield would be 98% if the defect rate of transistors is 5%, and 77% for 10% defective transistors.

[1]  Teng Wang,et al.  Latching on the wire and pipelining in nanoscale designs , 2004 .

[2]  Teng Wang,et al.  Opportunities and challenges in application-tuned circuits and architectures based on nanodevices , 2004, CF '04.

[3]  Seth Copen Goldstein,et al.  NanoFabrics: spatial computing using molecular electronics , 2001, Proceedings 28th Annual International Symposium on Computer Architecture.

[4]  Dongmok Whang,et al.  Large-scale hierarchical organization of nanowire arrays for integrated nanosystems , 2003 .

[5]  Charles M. Lieber,et al.  Growth and transport properties of complementary germanium nanowire field-effect transistors , 2004 .

[6]  Wei Lu,et al.  Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures , 2004 .

[7]  Charles M. Lieber,et al.  Logic Gates and Computation from Assembled Nanowire Building Blocks , 2001, Science.

[8]  M. Meyyappan,et al.  Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor , 2004 .

[9]  André DeHon,et al.  Nanowire-based programmable architectures , 2005, JETC.

[10]  C. Moritz,et al.  Towards Defect-Tolerant Nanoscale Architectures , 2006, 2006 Sixth IEEE Conference on Nanotechnology.

[11]  Csaba Andras Moritz,et al.  Wire-Streaming Processors on 2-D Nanowire Fabrics , 2005 .

[12]  Raphael Rubin,et al.  3D Nanowire-Based Programmable Logic , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[13]  David P. Norton,et al.  Depletion-mode ZnO nanowire field-effect transistor , 2004 .

[14]  D. Strukov,et al.  CMOL: Devices, Circuits, and Architectures , 2006 .

[15]  Csaba Andras Moritz,et al.  Combining Circuit Level and System Level Techniques for Defect-Tolerant Nanoscale Architectures , 2006 .

[16]  Teng Wang,et al.  Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Charles M. Lieber,et al.  Doping and Electrical Transport in Silicon Nanowires , 2000 .