Sub-10-ps gate delay by reducing the current crowding effect at an extension
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M. Ushiyama | J. Yugami | T. Shiba | K. Ohnishi | D. Hisamoto | K. Umeda
[1] Digh Hisamoto,et al. A low-resistance self-aligned T-shaped gate for high-performance sub-0.1-/spl mu/m CMOS , 1997 .
[2] K.K. Ng,et al. Analysis of the gate-voltage-dependent series resistance of MOSFET's , 1986, IEEE Transactions on Electron Devices.