Low-Voltage VLSI BiCMOS Circuit Design

BiCMOS technology offers enhanced performance compared to CMOS at 5 V power supply voltage. Many high-speed BiCMOS SRAMs, gate arrays, ASICs, etc. have been fabricated [1]. In this chapter, we present a variety of BiCMOS logic circuits suitable for 3.3 and sub-3.3 V. The potential gates for digital applications are identified. The chapter starts with the introduction of the conventional BiCMOS (totem-pole) gate which is used in 5 V applications. The degradation of this gate, with supply voltage scaling, is demonstrated. In Section 5.2, we introduce the BiNMOS family suitable for low-voltage applications. Other logic families, for low power supply voltage operation, are discussed in Section 5.3. Low-voltage digital applications of BiCMOS are identified. The reader is referred to BiCMOS books [2, 3] to get more familiar with BiCMOS circuits.

[1]  T. Enomoto,et al.  A 300-MHz 16-b BiCMOS video signal processor , 1993 .

[2]  A. El Gamal,et al.  BiNMOS: a basic cell for BiCMOS sea-of-gates , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[3]  Paul G. Y. Tsui,et al.  A fully complementary BiCMOS technology for sub-half-micrometer microprocessor applications , 1992 .

[4]  S.H.K. Embabi,et al.  A bootstrapped bipolar CMOS (B/sup 2/CMOS) Gate for low-voltage applications , 1995 .

[5]  Mohamed I. Elmasry,et al.  Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime , 1995 .

[6]  G. P. Rosseel,et al.  Influence of device parameters on the switching speed of BiCMOS buffers , 1989 .

[8]  Mohamed I. Elmasry,et al.  Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling , 1994 .

[9]  C.A.T. Salama,et al.  1.5 V bootstrapped BiCMOS logic gate , 1993 .

[10]  Kunihiko Yamaguchi,et al.  A 1.5 ns 256 kb BiCMOS SRAM with 11 k 60 ps logic gates , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[11]  Mohamed I. Elmasry,et al.  New full-voltage-swing BiCMOS buffers , 1991 .

[12]  K. Nakamura,et al.  A 5 ns 1 Mb ECL BiCMOS SRAM , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[13]  A. Bellaouar,et al.  BiCMOS at low supply voltage , 1993, 1993 Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

[14]  Katsuhiko Sato,et al.  An 8 ns 1 Mb ECL BiCMOS SRAM , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[15]  Fumio Murabayashi,et al.  A 0.5 μm BiCMOS channelless gate array , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[16]  S. Watanabe,et al.  BICMOS circuit technology for high speed DRAMs , 1987, 1987 Symposium on VLSI Circuits.

[17]  Y. Tsujihashi,et al.  A 64-bit adder by pass transistor BiCMOS circuit , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[18]  P. Raje,et al.  BiCMOS gate performance optimization using a unified delay model , 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

[19]  Hiroshi Iwai,et al.  A 350 ps 50 K 0.8 μm BiCMOS gate array with shared bipolar cell structure , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[20]  Takayasu Sakurai,et al.  0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file , 1992 .

[21]  Kenji Maeguchi,et al.  0.5/spl mu/m 2M-transistor BipnMOS Channelless Gate Array , 1991 .

[22]  K. Anami,et al.  A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancy , 1990, Digest of Technical Papers., 1990 Symposium on VLSI Circuits.

[23]  T. Yamazaki,et al.  A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator , 1994 .

[24]  Kiyoo Itoh,et al.  An experimental 1-Mbit BiCMOS DRAM , 1987 .

[25]  Krishna C. Saraswat,et al.  Performance-driven scaling of BiCMOS technology , 1992 .

[26]  Mohamed I. Elmasry,et al.  Analysis and optimization of BiCMOS digital circuit structures , 1991 .

[27]  Y. Maki,et al.  A 6.5 ns 1 Mb BiCMOS ECL SRAM , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[28]  A. R. Alvarez,et al.  BiCMOS technology and applications , 1990 .

[29]  Koichiro Mashiko,et al.  A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates , 1991 .

[30]  James D. Gallia,et al.  High-performance BiCMOS 100 K-gate array , 1990 .

[31]  Takashi Nishida,et al.  Quasi-complementary BiCMOS for sub-3-V digital circuits , 1991 .

[32]  Yoji Nishio,et al.  A BiCMOS logic gate with positive feedback , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[33]  Paul G. Y. Tsui,et al.  Study of BiCMOS logic gate configurations for improved low-voltage performance , 1993 .

[34]  Fumio Murabayashi,et al.  3.3 V, novel circuit techniques for a 2.8-million-transistor BiCMOS RISC processor , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[35]  Kazuo Yano,et al.  A 1.5-V full-swing BiCMOS logic circuit , 1992 .