Low-Complexity Solution for Highly Parallel Architecture

The complexity of highly parallel architecture depends on the parallelism, the area of a single SISO decoder, and the apparatus for parallel data transmission. Chapters 2 and 3 have given the guidelines of choosing proper processing schedule and normalization method of the SISO decoder. Thus, the focus of this chapter is on the circuits that interconnect SISO decoders and memory modules. The trivial apparatus is the fully-connected network. It can offer arbitrary one-to-one interconnection patterns.

[1]  Gianluca Piccinini,et al.  Architectural strategies for low-power VLSI turbo decoders , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Amer Baghdadi,et al.  Butterfly and Benes-Based on-Chip Communication Networks for Multiprocessor Turbo Decoding , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[3]  Cheng-Chi Wong,et al.  Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture , 2010, IEEE Journal of Solid-State Circuits.

[4]  Cheng-Chi Wong,et al.  Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Paul Fortier,et al.  Highly-Parallel Decoding Architectures for Convolutional Turbo Codes , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Yeheskel Bar-Ness,et al.  A parallel MAP algorithm for low latency turbo decoding , 2002, IEEE Communications Letters.

[7]  Qiuting Huang,et al.  Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE , 2011, IEEE Journal of Solid-State Circuits.