Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication Systems

Explicitly multithreaded processors and reconfigurable hardware have individually proven to be useful in the design of wireless communication systems. However, new techniques are needed to satisfy the processing requirements of emerging wireless communication standards, which have high throughput requirements for a wide variety of algorithms. This paper presents an efficient technique for adding reconfigurable functional units, called Polymorphic Hardware Accelerators (PHAs), to multicore, multithreaded Digital Signal Processors (DSPs). This paper discusses architectural support to facilitate management and sharing of PHAs on a multithreaded system. The proposed technique shows an average speedup of 6.8 on important wireless communication algorithms in the EEMBC Telecom Benchmark Suite and Department of Defense's Joint Tactical Radio System Software Communication Architecture (JTRS SCA) Hardware Supplement.

[1]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[2]  Stamatis Vassiliadis,et al.  The MOLEN polymorphic processor , 2004, IEEE Transactions on Computers.

[3]  Roberto Guerrieri,et al.  A XiRisc-based SoC for embedded DSP applications , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[4]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, ISCA '00.

[5]  Stamatis Vassiliadis,et al.  The MOLEN processor prototype , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[6]  Jeffrey M. Arnold,et al.  S5: the architecture and development flow of a software configurable processor , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[7]  Jason Cong,et al.  Application-specific instruction generation for configurable processor architectures , 2004, FPGA '04.

[8]  D. Tabak,et al.  A multiple context reconfigurable functional unit , 2001, Proceedings Euromicro Symposium on Digital Systems Design.

[9]  Olli Silvén,et al.  Observations on Power-Efficiency Trends in Mobile Communication Devices , 2005, SAMOS.

[10]  A.R. Weiss.  The standardization of embedded benchmarking: pitfalls and opportunities , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[11]  Nathan Clark,et al.  An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors , 2005, ISCA 2005.

[12]  Ralph Wittig,et al.  OneChip: an FPGA processor with reconfigurable logic , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[13]  Stamatis Vassiliadis,et al.  A Low-Power Multithreaded Processor for Baseband Communication Systems , 2004, SAMOS.

[14]  Scott Hauck,et al.  The Chimaera reconfigurable functional unit , 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.