Practical Fast Clock-Schedule Design Algorithms

In this paper, a practical clock-scheduling engine is introduced. The minimum feasible clock-period is obtained by using a modified Bellman-Ford shortest path algorithm. Then an optimum cost clock-schedule is obtained by using a bipartite matching algorithm. It also provides useful information to circuit synthesis tools. The experiment to a circuit with about 10000 registers and 100000 signal paths shows that a result is obtained within a few minutes. The computation time is almost linear to the circuit size in practice.

[1]  Andrew V. Goldberg,et al.  Negative-cycle detection algorithms , 1996, Math. Program..

[2]  Eby G. Friedman,et al.  Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[3]  Atsushi Takahashi,et al.  Clock Schedule Design for Minimum Realization Cost , 2000 .

[4]  Robert K. Brayton,et al.  Graph algorithms for clock schedule optimization , 1992, ICCAD.

[5]  Wayne Wei-Ming Dai,et al.  Jitter-tolerant clock routing in two-phase synchronous systems , 1996, Proceedings of International Conference on Computer Aided Design.

[6]  Richard M. Karp,et al.  A characterization of the minimum cycle mean in a digraph , 1978, Discret. Math..

[7]  Eby G. Friedman,et al.  Clock skew scheduling for improved reliability via quadratic programming , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[8]  Robert E. Tarjan,et al.  Faster parametric shortest path and minimum-balance algorithms , 1991, Networks.

[9]  Eby G. Friedman,et al.  Optimal clock skew scheduling tolerant to process variations , 1996, DAC '96.

[10]  Atsushi Takahashi,et al.  Performance and reliability driven clock scheduling of sequential logic circuits , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[12]  Sachin S. Sapatnekar,et al.  A graph-theoretic approach to clock skew optimization , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[13]  Thomas G. Szymanski,et al.  Computing optimal clock schedules , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[14]  Wayne W.-M. Dai,et al.  Jitter-tolerant clock routing in two-phase synchronous systems , 1996, ICCAD 1996.

[15]  Jens Vygen,et al.  Cycle time and slack optimization for VLSI-chips , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[16]  Sachin S. Sapatnekar,et al.  Clock Skew Optimization , 1999 .