Analysis and design of class-B dual fed distributed power amplifiers

The analysis of, and derivation of design equations for, a class-B balanced single-ended dual-fed distributed amplifier is presented. This approach allows efficient combining of FET output power without multi-way power combiners, has a good port match, and is easy to design as the gate and drain transmission lines are uniform. The design method ensures that all FETs are optimally used and the efficiency is comparable to that of a conventional single-transistor class-B power amplifier using the same FET type. The design method was applied to a class-B four-FET balanced single-ended dual-fed distributed amplifier designed to operate at 1.8 GHz. Large-signal measurements revealed 8% downward shift of the centre frequency. The measured output power and drain efficiency was consistent with the simulations. The efficiency of the amplifier was comparable to a conventional single-transistor class-B power amplifier using the same type of FET.

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