Evaluation of Routing Algorithms on Mesh Based NoCs

The increasing complexity of integrated circuits drives the research of new on-chip interconnection architectures. Networks-on-chip (NoCs) are a candidate architecture to be used in future systems, due to its increased performance, reusability and scalability. A NoC is a set of interconnected switches, with IP cores connected to these switches. Four main components compose a switch: a router, to define a path between input and output switch ports; an arbiter, to grant access to a given port when multiple input requests arrive in parallel; buffers, to store intermediate data, and a flow control module to regulate the data transfer to the next switch. The goal of this work is to compare the performance of four routing algorithms for mesh based packet switching NoCs. Differently from the literature for generic networks, it is shown that deterministic algorithms can be superior to adaptive ones in NoCs.

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