A Novel Compact Model for the Drift Region of LDMOS Devices

A novel compact model for the drift region of LDMOS devices is presented in this paper. According to a surface potential-based description of the drift region of LDMOS devices underneath the gate oxide, the proposed model gives a complete description for all operation regimes in this region, while keeping a relatively simplified analytical expression of current. The proposed drift region model is verified against the measured data of the actual LDMOS device. The comparison results demonstrate that the new model gives an accurate description for electronic characteristics of LDMOS transistors.