Comparative analysis of digital IIR filter using add and shift method on Xilinx platform

This paper describes a method for implementing a digital Infinite Impulse Response (IIR) filters using different registered adders and shift method to improve occupied area and delay. Canonical Signed Digit (CSD) representation for defined filter coefficients has been extensively used to reduce the number of adders. The method using different adders is effectively applied to a four-order IIR filter. The performance of IIR filter using parallel prefix adders is compared with the filter using Ripple Carry Adder. Number of additions has been reduced to 33% by using CSD representation as compared to Binary representation. The proposed IIR filters are synthesized and implemented using Xilinx ISE Simulator. The designs perform significantly better than conventional IIR filters.

[1]  Avinash Shrivastava,et al.  Design and Estimation of delay, power and area for Parallel prefix adders , 2017 .

[2]  M. Mohamed Asan Basiri,et al.  Configurable Folded IIR Filter Design , 2015, IEEE Trans. Circuits Syst. II Express Briefs.

[3]  Sunil P. Khatri,et al.  A Timing-Driven Approach to Synthesize Fast Barrel Shifters , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Michael Francis.  Infinite Impulse Response Filter Structures in Xilinx FPGAs , 2008 .

[5]  P. R. Mahalingam,et al.  Adapting Barrel Shifter at Compilation Level for Efficient Implementation of Multiplications , 2012, 2012 International Conference on Advances in Computing and Communications.

[6]  M. Tech.  Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tree and Brentkung Adders , 2013 .

[7]  R. Nagendra,et al.  Design of 32 bit Parallel Prefix Adders , 2013 .

[8]  M MohamedAsanBasiri,et al.  Configurable Folded IIR Filter Design , 2015 .

[9]  S PremanandaB,et al.  DESIGN AND IMPLEMENTATION OF FASTER PARALLEL PREFIX KOGGE STONE ADDER , 2014 .

[10]  Swapna K. Gedam,et al.  PARALLEL PREFIX HAN-CARLSON ADDER , 2014 .

[12]  R. M. Hewlitt,et al.  Canonical signed digit representation for FIR digital filters , 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

[13]  In-Cheol Park,et al.  FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Ryan Kastner,et al.  FPGA Implementation of High Speed FIR Filters Using Add and Shift Method , 2006, 2006 International Conference on Computer Design.