Design and verification of high‐throughput IEEE 802.11 MAC‐layer hardware IP with FPGA platform

Abstract The development of a high‐throughput and low‐cost medium access control (MAC) layer design is a very important issue for wireless local area network (WLAN) communication. In this paper, the proposed MAC‐layer hardware architecture is simplified by using a small number of finite state machines (FSMs) and a low‐latency parallel processing architecture. The FSMs on both the transmitter (TX) and receiver (RX) sides can be operated at low power. In the MAC‐layer receiver, an efficient low‐complexity timestamp controller is proposed for fast timing synchronization. We implement the distributed coordination function (DCF) of the MAC protocol in IEEE 802.11a/b/g standards within the ad‐hoc configuration. The proposed MAC‐layer hardware is implemented with Xilinx XC4VLX60 FPGA, the hardware area needs 5944 slices, and the effective throughput is 147.6 Mbps. With TSMC 0.18 μm CMOS process, the effective throughput at the maximum working frequency 83.3 MHz is 299.88 Mbps, which is larger than the standard IEEE 802.11 g requirement, i.e. 54 Mbps.