论文信息 - An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS

An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS

This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The 17-mm/sup 2/ device is implemented in a 0.25-/spl mu/m CMOS process, operates off of 2.5- and 3.3-V supply voltages, and consumes 1 W.

Gu-Yeon Wei | John T. Stonick | Jeffrey L. Sonntag | Daniel Keith Weinlader

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