Automatic design of binary and multiple-valued logic gates on RTD series

In this paper, we contribute to the binary and multiple-valued applications of resonant tunneling devices (RTDs). We propose a method of systematic design of physical parameters of RTD based logic. From the abstraction of their behavior, we model the design space as a handful of systems of linear inequalities generated for a given circuit topology and an arbitrary logic function. Any valid solution reflects the physical parameters assignment that implements the function given. We solve these systems using off-the-shelf optimization tool and verify the results using SystemC based RTD circuit model. Our simulations confirm that the numerical solutions are valid parameter assignments.