Optimum wordlength allocation

This paper presents an approach to the wordlength allocation and optimization problem for linear digital signal processing systems implemented in Field-Programmable Gate Arrays. The proposed technique guarantees an optimum set of wordlengths for each internal variable, allowing the user to trade-off implementation area for error at system outputs. Optimality is guaranteed through modelling as a mixed integer linear program, constructed through novel techniques for the linearization of error and area constraints. Optimum results in this field are valuable since they can be used to assess the effectiveness of heuristic wordlength optimization techniques. It is demonstrated that one such previously published heuristic reaches within 0.7% of the optimum area over a range of benchmark problems.

[1]  W. Luk,et al.  Truncation noise in fixed-point SFGs , 1999 .

[2]  Stephen A. Dyer,et al.  Digital signal processing , 2018, 8th International Multitopic Conference, 2004. Proceedings of INMIC 2004..

[3]  Pheng-Ann Heng,et al.  Automatic floating to fixed point translation and its application to post-rendering 3D warping , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[4]  P. Perona,et al.  Bit-width optimization for configurable DSP's by multi-interval analysis , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

[5]  Mark Stephenson,et al.  Bidwidth analysis with application to silicon compilation , 2000, PLDI '00.

[6]  Alok N. Choudhary,et al.  Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[7]  Wayne Luk,et al.  Roundoff-noise shaping in filter design , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[8]  Wayne Luk,et al.  The Multiple Wordlength Paradigm , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[9]  Scott McMillan,et al.  A re-evaluation of the practicality of floating-point operations on FPGAs , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[10]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[11]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[12]  Gerhard J. Woeginger,et al.  The complexity of multiple wordlength assignment , 2002, Appl. Math. Lett..

[13]  G. Nemhauser,et al.  Integer Programming , 2020 .

[14]  W. Luk,et al.  Truncation noise in fixed-point SFGs [digital filters] , 1999 .

[15]  Alice C. Parker,et al.  Accuracy sensitive word-length selection for algorithm optimization , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[16]  Patrick Schaumont,et al.  A methodology and design environment for DSP ASIC fixed point refinement , 1999, DATE '99.

[17]  R. Cmar,et al.  A methodology and design environment for DSP ASIC fixed point refinement , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).