Hierarchical Watermarking Method for FPGA IP Protection

Abstract With the increasing intellectual property (IP) abuse in System-on-a-Chip design, watermarking technique is playing an important role for IP protection. In this paper, we combine watermarking methods at different levels to construct a hierarchical watermarking scheme for field programmable gate array (FPGA) IP protection. We first embed the watermark into the netlist by using a look-up table-SRL transformation. Then we embed the watermark into the bitstream of the same design by using JBits. We test our method on three public FPGA benchmarks. The experimental results show that the overhead of watermarking is significantly reduced due to our judicious strategies. The watermark embedded at high level is well propagated to lower level. Our technique provides a robust and secure watermarking solution.

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