Test structure definition for dummy metal filling strategy dedicated to advanced integrated RF inductors

A complete strategy to manage dummy fills inside a large spectrum of integrated RF inductors realized in a 0.13 mum CMOS technology using a dual damascene copper back end of line (BEOL) is presented here. Thanks to the developed test structures, their RF characterization, and a design of experiment (DOE) modeling analysis, it has been possible to determine the right metal fill density to insert inside inductors in order to be compliant with digital metal density rules without degrading their electrical performances.

[1]  C. Yue,et al.  On-chip Spiral Inductors With Patterned Ground Shields For Si-based RF IC's , 1997, Symposium 1997 on VLSI Circuits.

[2]  L.F. Tiemeijer,et al.  Physics-based wideband predictive compact model for inductors with high amounts of dummy metal fill , 2006, IEEE Transactions on Microwave Theory and Techniques.

[3]  Duane S. Boning,et al.  PATTERN AND PROCESS DEPENDENCIES IN COPPER DAMASCENE CHEMICAL MECHANICAL POLISHING PROCESSES , 1998 .

[4]  Torben Larsen,et al.  Ground-shielded measuring technique for accurate on-wafer characterization of RF CMOS devices , 2000, ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095).

[5]  Troels Emil Kolding On-wafer calibration techniques for giga-hertz CMOS measurements , 1999, ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307).

[6]  Andrew B. Kahng,et al.  Filling algorithms and analyses for layout density control , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Yong-Zhong Xiong,et al.  Experimental Characterization of the Effect of Metal Dummy Fills on Spiral Inductors , 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.