An Efficient Low-Swing Multithreshold-Voltage Low-Power Design Technique

New low-power design architecture based on low-swing voltage technique is proposed in this paper. A new CMOS inverter of three output-voltage levels is used to achieve this target. To verify the validity of the proposed technique, three different logic families are used. SPICE simulation results for the three logic families show that more than 45% power dissipation can be saved, without sacrifice the speed operation. Comparison results between the proposed technique and other techniques based on low-swing voltage, shown the superiority of our technique in reducing the power dissipation. Based on 2.4 V supply voltage, a 16 * 16-bit multiplier is implemented by using the proposed technique in 0.25μm silicon technology.

[1]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[2]  Anantha P. Chandrakasan,et al.  A low power chipset for portable multimedia applications , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[3]  Anantha Chandrakasan,et al.  Low Power Techniques for Portable Real-time DSP Applications , 1992, The Fifth International Conference on VLSI Design.

[4]  Anantha P. Chandrakasan,et al.  Design of portable systems , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[5]  Anantha P. Chandrakasan,et al.  Low-Power CMOS Design , 1997 .

[6]  Jan M. Rabaey,et al.  Power estimation for high level synthesis , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[7]  Maarten Kuijk,et al.  A 900-Mb/s CMOS data recovery DLL using half-frequency clock , 2002 .

[8]  A. M. Fahim,et al.  Low-power high-performance arithmetic circuits and architectures , 2002 .

[9]  Sung-Mo Kang,et al.  A low-swing clock double-edge triggered flip-flop , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[10]  Soha Hassoun,et al.  A 200-MHz 64-bit Dual-Issue CMOS Microprocessor , 1992, Digit. Tech. J..

[11]  Chih-Ming Hung,et al.  Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters , 2002, IEEE J. Solid State Circuits.

[12]  Abdoul Rjoub,et al.  Multiple low swing voltage values for CPL, CVSL and domino logic families , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).