An analog VLSI chip with asynchronous interface for auditory feature extraction

We describe the architecture and circuit implementation of an analog VLSI feature extraction chip that has an asynchronous digital interface and is designed to serve as an auditory based front-end for a digit recognition system. The single chip system encodes signal energies and zero crossing time intervals of frequency components in a cochlear filter bank. The chip has been fabricated in a 1.2 /spl mu/m n-well, double polysilicon, double metal CMOS process and it is fully functional. Power consumption when operated from a 5 V supply is only a few milliwatts.

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