Two-dimensional dynamic graphs and their vlsi applications

This thesis deals with problems related to the design of highly regular VLSI chips. We treat these problems from both a practical and theoretical point of view. The first part of the thesis deals with the optimization of leaf cells either isolated or embedded in regular arrays. We develop what we call the critical-path optimization method for finding locally optimal cells in large arrays, with the criterion of speed and power consumption. Experimental results are given for the optimization of an array multiplier consisting of identical one-bit full adders. In order to make the optimization of very large array multipliers practical, we develop what we call the canonical configuration method. This method generates the critical path of any large array multiplier from the critical paths which appear in some array of fixed size. This allows us to optimize any large array multiplier in time independent of the size of the array. The second part of the thesis deals with theoretical aspects of the problems and techniques of the first part. A two-dimensional dynamic graph is a locally-finite, infinite graph comprised of identical finite graphs at every integer orthogonal grid point in the Euclidean plane and edges which connect these finite graphs in a regular pattern. First, we solve the acyclicity problem for dynamic graphs by using a semiring defined on the set of convex polygons with respect to two operations: vector summation and convex hull of the union. Second, we study problems of planarity testing, weak connectivity, finding an Eulerian path, and testing 2-colorability of dynamic graphs. Instead of solving these problems for infinite dynamic graphs, we reduce these to problems for finite graphs by making use of regularity. Finally, we investigate the longest path problem for dynamic graphs. We re-define the canonical configuration in terms of dynamic graphs and investigate why and when the canonical configuration becomes practical.