High-Level Performance Estimation Using Simulators At Multiple Abstraction Levels

Design Space Exploration (DSE) of an application running on a Multi-Processor System-on-Chip (MPSoC) platform is a challenging task. In order to tackle this DSE challenge, fast high-level simulators (running at multiple abstraction levels) are used to provide static and dynamic evaluation of the system-level performance metrics (e.g. execution time, energy consumption). These simulators are coupled with advanced DSE tools to generate Pareto set of optimum system configurations for a specified application running on a specified MPSoC platform. This generated Pareto set is used by a Run-Time Manager to optimize platform resource usage during the application run. DSE for an application requires a large number of application runs. There is a trade-off between accuracy of the simulation results and the time taken for simulating application. Using simulators at multiple abstraction levels allows the application developer to make this trade-off (between simulation accuracy and simulation time). DSE is done with a large set of application runs using faster higher-level simulators (e.g.IMEC-HLsim [1] and MULTICUBE-SCoPE [2]). The DSE end results (Pareto set of optimum operating points for the application) are verified using more accurate platform simulators (e.g. cycle-accurate simulators built using CoWare Virtual Platform tool [3]). To enable seamless integration of DSE results across multiple simulators, a generic XML interface between DSE tools and simulators is defined [4]. This XML interface defines the format of system-level performance metrics used as an input-output by each simulator. Further, the XML interface specifies the design space that can be explored by the DSE tools at all the abstraction levels.