Performance Evaluation of Different Hardware Models of RC5 Algorithm

Nowadays transmitting data securely over a network is gaining more and more importance and is triggering a need for an improvement in performance of the encryption algorithms. Even though the software implementation has the advantages of portability, flexibility and ease of use it provides a limited physical security as well as agility. When compared to the software implementation, the hardware implementation is having positive features like improvement in operating speed and security. The other advantages that lead to the hardware implementation are less power consumption, allocation of resources, re-configurability, architecture efficiency and cost efficiency. This paper presents a performance evaluation of two hardware models of RC5 algorithm. Evaluations will be used to determine the best hardware model for two different system requirements.

[1]  Jean-Didier Legat,et al.  Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis , 2003, IEEE Trans. Computers.

[2]  H.M. Heys,et al.  The FPGA implementation of the RC6 and CAST-256 encryption algorithms , 1999, Engineering Solutions for the Next Millennium. 1999 IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.99TH8411).

[3]  Ronald L. Rivest,et al.  The RC5 Encryption Algorithm , 1994, FSE.

[4]  Christof Paar,et al.  An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Christof Paar,et al.  An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists , 2000, AES Candidate Conference.

[6]  Odysseas G. Koufopavlou,et al.  Mobile Communications World: Security Implementations Aspects - A State of the Art , 2003, Comput. Sci. J. Moldova.

[7]  Odysseas G. Koufopavlou,et al.  Area optimized architecture and VLSI implementation of RC5 encryption algorithm , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

[8]  Walter Anheier,et al.  Efficient VLSI implementation of modern symmetric block ciphers , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).