State of the Art Pipelined ADC Design

An overview of several state of the art design techniques in achieving good linearity and low power in pipelined ADCs are outlined. Digital calibration is shown as a technique to improve non-idealities which arise due to low DC gain in opamps, and capacitor mismatch in pipelined ADCs. Techniques to reduce ADC power discussed include the elimination of the front-end S/H, open-loop amplifier approaches, and comparator based switched capacitor circuits.

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