LVS Method for Yield Analysis Chip

The characters and design flow of yield analysis chip are studied.Yield analysis chip contains special components with violation of design rules and mismatch of layout and schematic,so a new method is presented which is the combination of traditional Layout Versus Schematic(LVS) method and formal verification.Yield analysis chip is designed and verified under the new flow.Experimental result shows that the verification process of yield analysis chip is right and stable.