A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support

The scaling of CMOS technology together with continued innovations in circuit and system design techniques is fueling a rising demand for increasingly high throughput serial data interfaces. However, advances in CMOS technology have little impact on channel performance, making channel impairments a bottleneck in wireline links. Furthermore, links are typically designed to cover multiple standards and are expected to operate over a wide range of data rates, making their design challenging [1-5]. This work presents a 4-lane 1.25–28.05Gb/s transceiver in 14nm FinFet technology. We measure a bit error rate (BER) lower than 1e-15 with a channel loss of 40dB at 28.05Gb/s.

[1]  Thomas Toifl,et al.  A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology , 2012, 2012 IEEE International Solid-State Circuits Conference.

[2]  Pervez M. Aziz,et al.  A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.

[3]  Keiichi Higeta,et al.  3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[4]  Amaresh Malipatil,et al.  2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[5]  Hiva Hedayati,et al.  3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[6]  Sanjeev K. Maheshwari,et al.  An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors , 2012, IEEE Journal of Solid-State Circuits.