The use of the rademacher-walsh spectrum for data compression in logic testing

The testing of logic circuits is accomplished by applying test stimuli and checking the response of the unit under test against that of the good unit. In compact testing the test response is compressed and compared against the "signature" of the good unit. The technique is particularly appropriate for field testing of bus oriented systems to isolate hardware failures down to the chip-level. This thesis studies the use of the Rademacher-Walsh spectral techniques for compact testing of digital logic. These techniques are well known in the analog domain but their use in the digital domain is relatively recent. We identify the spectral properties which relate to testing and testable designs. It is shown that the parity of the function weight plays an important role in improving the testability of the circuit using the spectral techniques. Both deterministic and random compact testing methods are considered. For deterministic testing several commonly applicable fault models are considered and guidelines provided for choosing one or two spectral coefficients for data compression. The results lead to a suggestion for improving the testability of two-level circuits, such as the programmable logic arrays (PLA's). Two measures of performance of random compact testing are considered: the probability of rejecting a good unit and the probability of accepting a faulty unit. A new test scheme is proposed to improve the performance of random compact testing using a spectral coefficients, and a mathematical analysis is given for determining the performance.