A 6-bit 4 MS/s, VCM-based sub-radix-2 SAR ADC with inverter type comparator

This paper presents a 6-bit sub-radix-2 redundant VCM-based SAR ADC for BLE transceiver applications. The basic trend for BLE applications is to reduce area and power consumption. In order to reduce switching power consumption, VCM-based straightforward CDAC is applied. Custom-designed 600aF unit capacitor minimizes the area and analog power consumption of the ADC. Sub-radix-2 redundant architecture, as well as digital calibration, is applied for CDAC which guarantees digitally correctable static nonlinearities of the converter and dynamic errors in the conversion process occurs due to small capacitor sizes. The structure applies an inverter type comparator to reduce the area. The prototype ADC is fabricated and measured in a 55nm CMOS process and achieves 5.315.89 ENOB at 4 MS/s sampling frequency. SNDR and SFDR for Nyquist input frequency are 33.73dB and 40.2dB respectively. The current consumption is 3.7A from a 1.0V supply, which corresponds to 23 fJ/step FOM. The active area of the core ADC is 100m45m.

[1]  Arthur H. M. van Roermund,et al.  11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[2]  Ho-Jin Park,et al.  A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC , 2015, IEEE Journal of Solid-State Circuits.

[3]  Zhangming Zhu,et al.  A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- μm CMOS for Medical Implant Devices. , 2015 .

[4]  V. Chaturvedi,et al.  Energy efficient asymmetric binary search switching technique for SAR ADC , 2010 .

[5]  Takaya Yamamoto,et al.  A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver , 2013, IEEE Journal of Solid-State Circuits.

[6]  Wei-Liang Lin,et al.  An 11-Bit Single-Ended SAR ADC with an Inverter-Based Comparator for Design Automation , 2016, IEICE Trans. Electron..

[7]  Zhangming Zhu,et al.  A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Yvonne Y. H. Lam,et al.  Low-energy and area-efficient tri-level switching scheme for SAR ADC , 2012 .

[9]  G. Wen,et al.  Energy-efficient hybrid capacitor switching scheme for SAR ADC , 2014 .

[10]  Jon Guerber,et al.  Merged capacitor switching based SAR ADC with highest switching energy-efficiency , 2010 .

[11]  Zhangming Zhu,et al.  A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-$\mu{\rm m}$ CMOS for Medical Implant Devices , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Zhangming Zhu,et al.  V CM -based monotonic capacitor switching scheme for SAR ADC , 2013 .

[13]  Chih-Cheng Hsieh,et al.  A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[14]  Sang-Hyun Cho,et al.  A 550-$\mu\hbox{W}$ 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction , 2011, IEEE Journal of Solid-State Circuits.

[15]  Gabor C. Temes,et al.  Multi-step capacitor-splitting SAR ADC , 2010 .

[16]  Michail Papamichail,et al.  A 10 mW Bluetooth Low-Energy Transceiver With On-Chip Matching , 2015, IEEE Journal of Solid-State Circuits.

[17]  N. P. van der Meijs,et al.  A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios , 2011, IEEE Journal of Solid-State Circuits.

[18]  Zhangming Zhu,et al.  A 67.2 dB SNDR 1.8-V 12-bit 2-MS/s SAR ADC without calibration , 2016 .

[19]  Yan Zhang,et al.  A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step , 2012, 2012 IEEE International Solid-State Circuits Conference.

[20]  Atila Alvandpour,et al.  Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[21]  Hoi-Jun Yoo,et al.  An energy-efficient dual sampling SAR ADC with reduced capacitive DAC , 2009, 2009 IEEE International Symposium on Circuits and Systems.