Caches often employ write-back instead of write-through, since write-back avoids unnecessary transfers for multiple writes to the same block. For several reasons, however, it is undesirable that a significant number of cache lines will be marked ldquodirtyrdquo. Energy-efficient cache organizations, for example, often apply techniques that resize, reconfigure, or turn off (parts of) the cache. In such cache organizations, dirty lines have to be written back before the cache is reconfigured. The delay imposed by these write-backs or the required additional logic and buffers can significantly reduce the attained energy savings. A cache organization called the clean/dirty cache (CD-cache) is proposed that combines the properties of write-back and write-through. It avoids unnecessary transfers for recurring writes, while restricting the number of dirty lines to a hard limit. Detailed experimental results show that the CD-cache reduces the number of dirty lines significantly, while achieving similar or better performance. We also use the CD-cache to implement cache decay. Experimental results show that the CD-cache attains similar or higher performance than a normal decay cache, while using a significantly less complex design.
[1]
Kaushik Roy,et al.
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
,
2000,
ISLPED '00.
[2]
G. Tyson,et al.
Eager writeback-a technique for improving bandwidth utilization
,
2000,
Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.
[3]
Margaret Martonosi,et al.
Let caches decay: reducing leakage energy via exploitation of cache generational behavior
,
2002,
TOCS.
[4]
Norman P. Jouppi,et al.
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
,
1990,
[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[5]
Norman P. Jouppi.
Cache write policies and performance
,
1993,
ISCA '93.
[6]
William H. Mangione-Smith,et al.
The filter cache: an energy efficient memory structure
,
1997,
Proceedings of 30th Annual International Symposium on Microarchitecture.
[7]
Pong P. Chu,et al.
Write buffer design for on-chip cache
,
1994,
Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.