Throughput-delay analysis of interrupt-driven kernels with DMA enabled and disabled in high-speed networks

Interrupt processing can be a major bottleneck in the end-to-end performance of high-speed networks. The performance of Gigabit network end hosts or servers can be severely degraded due to interrupt overhead caused by heavy incoming traffic. Under heavy network traffic, the system performance will be negatively affected due to interrupt overhead caused by the incoming traffic. In particular, excessive latency and significant degradation in system throughput can be experienced. In this paper, we present a throughput-delay analysis of such behavior. We develop analytical models based on queueing theory and Markov processes. In our analysis, we consider and model three systems: ideal, PIO, and DMA. In ideal system, the interrupt overhead is ignored. In PIO, DMA is disabled and copying of incoming packets is performed by the CPU. In DMA, copying of incoming packet is performed by DMA engines. For high-speed network hosts, both PIO and DMA can be desirable configuration options. The analysis yields insight into understanding and predicting the impact of system and network choices on the performance of interrupt-driven systems when subjected to light and heavy network loads. Simulations and reported experimental results show that our analytical models are valid and give a good approximation.

[1]  Murad S. Taqqu,et al.  On the Self-Similar Nature of Ethernet Traffic , 1993, SIGCOMM.

[2]  Parameswaran Ramanathan,et al.  HIP: hybrid interrupt-polling for the network interface , 2001, OPSR.

[3]  K. K. Ramakrishnan,et al.  Eliminating receive livelock in an interrupt-driven kernel , 1996, TOCS.

[4]  Hsiao-Keng Jerry Chu,et al.  Zero-Copy TCP in Solaris , 1996, USENIX Annual Technical Conference.

[5]  Averill M. Law,et al.  Simulation Modeling and Analysis , 1982 .

[6]  K. El-Badawi,et al.  Analysis and simulation of interrupt overhead impact on OS throughput in high‐speed networks , 2005, Int. J. Commun. Syst..

[7]  J.M. Smith,et al.  Giving applications access to Gb/s networking , 1993, IEEE Network.

[8]  Peter Druschel,et al.  Lazy receiver processing (LRP): a network subsystem architecture for server systems , 1996, OSDI '96.

[9]  Khaled Salah,et al.  Performance evaluation of interrupt-driven kernels in gigabit networks , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[10]  Alessandro Rubini,et al.  Linux device drivers - covers Linux 2.4 (2. ed.) , 2001 .

[11]  Dhabaleswar K. Panda,et al.  EMP: Zero-Copy OS-Bypass NIC-Driven Gigabit Ethernet Message Passing , 2001, ACM/IEEE SC 2001 Conference (SC'01).

[12]  Walter Willinger,et al.  On the self-similar nature of Ethernet traffic , 1993, SIGCOMM '93.

[13]  Peter Druschel,et al.  Operating system support for high-speed communication , 1996, CACM.

[14]  Leonard Kleinrock,et al.  Theory, Volume 1, Queueing Systems , 1975 .

[15]  K. K. Ramakrishnan,et al.  Performance Considerations in Designing Network Interfaces , 1993, IEEE J. Sel. Areas Commun..

[16]  Jonathan M. Smith,et al.  Hardware/Software Organization of a High-Performance ATM Host Interface , 1993, IEEE J. Sel. Areas Commun..

[17]  Jeffrey S. Chase,et al.  Trapeze / IP : TCP / IP at Near-Gigabit Speeds , 1999 .

[18]  K. Preston White,et al.  An Effective Truncation Heuristic for Bias Reduction in Simulation Output , 1997, Simul..

[19]  Peter Steenkiste.  A systematic approach to host interface design for high-speed networks , 1994, Computer.

[20]  EDDIE KOHLER,et al.  The click modular router , 2000, TOCS.

[21]  José Carlos Brustoloni,et al.  Effects of buffering semantics on I/O performance , 1996, OSDI '96.

[22]  Guru M. Parulkar,et al.  The APIC approach to high performance network interface design: protected DMA and other techniques , 1997, Proceedings of INFOCOM '97.