Delay control circuit and semiconductor memory device including the same

PURPOSE: A delay control circuit and a semiconductor memory device including the same are provided to generate a latency signal without errors at an accurate timing by controlling a replica delay amount of the delay control circuit. CONSTITUTION: A first replica delay unit(301) has a replica delay amount obtained by modeling a delay amount in a chip. A delay control unit(303) controls the replica delay amount according to the latency of an input signal. A measuring unit(113) generates path information by measuring a first delay amount and the replica delay amount. An operating unit(115) generates delay information using the path information and the latency of the input signal. A latency delay unit(117) generates a latency signal by delaying the input signal delayed by a first delay unit to correspond to the delay information. [Reference numerals] (101) Second delay unit(A); (103) Second replica delay unit(B); (105) Phase comparing unit; (109) First delay unit(A); (113) Measuring unit; (115) Operating unit; (117) Latency delay unit; (301) First replica delay unit; (303) Delay control unit