Detecting computer-induced errors in remote-sensing JPEG compression algorithms

The JPEG image compression standard is very sensitive to errors. Even though it contains error resilience features, it cannot easily cope with induced errors from computer soft faults prevalent in remote-sensing applications. Hence, new fault tolerance detection methods are developed to sense the soft errors in major parts of the system while also protecting data across the boundaries where data flow from one subsystem to the other. The design goal is to guarantee no compressed or decompressed data contain computer-induced errors without detection. Detection methods are expressed at the algorithm level so that a wide range of hardware and software implementation techniques can be covered by the fault tolerance procedures while still maintaining the JPEG output format. The major subsystems to be addressed are the discrete cosine transform, quantizer, entropy coding, and packet assembly. Each error detection method is determined by the data representations within the subsystem or across the boundaries. They vary from real number parities in the DCT to bit-level residue codes in the quantizer, cyclic redundancy check parities for entropy coding, and packet assembly. The simulation results verify detection performances even across boundaries while also examining roundoff noise effects in detecting computer-induced errors in processing steps.

[1]  M. Tsunoyama,et al.  A fault-tolerant FFT processor , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

[2]  Michael N. Lovellette,et al.  Implications of the different classes of exceptions experienced during the cots processor test flight on the argos satellite , 2003, 2003 IEEE Aerospace Conference Proceedings (Cat. No.03TH8652).

[3]  Alan Messer,et al.  Susceptibility of commodity systems and software to memory soft errors , 2004, IEEE Transactions on Computers.

[4]  Cristian Constantinescu,et al.  Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.

[5]  G. Robert Redinbo Concurrent error detection in fast unitary transform algorithms , 2001, 2001 International Conference on Dependable Systems and Networks.

[6]  P. Wintz Transform picture coding , 1972 .

[7]  D. S. Walsh,et al.  Single-event upset and snapback in silicon-on-insulator devices and integrated circuits , 2000 .

[8]  Fabrizio Lombardi,et al.  Concurrent error detection and fault location in an FFT architecture , 1992 .

[9]  S. Dodunekov,et al.  Undetected error probability performance of cyclic redundancy-check codes of 16-bit redundancy , 2000 .

[10]  Dilip V. Sarwate Computation of cyclic redundancy checks via table look-up , 1988, CACM.

[11]  Joan L. Mitchell,et al.  JPEG: Still Image Data Compression Standard , 1992 .

[12]  G. Ryan,et al.  A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC) , 1997, Proceedings VHDL International Users' Forum. Fall Conference.

[13]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[14]  Jacob A. Abraham,et al.  Fault-Tolerant FFT Networks , 1988, IEEE Trans. Computers.

[15]  Elizabeth M. Rudnick,et al.  A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults , 1996, IEEE Trans. Computers.

[16]  Tenkasi V. Ramabadran,et al.  A tutorial on CRC computations , 1988, IEEE Micro.

[17]  Magdy A. Bayoumi,et al.  Design and implementaion of a 2D-DCT architecture using coefficient distributed arithmetic [implementaion read implementation] , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

[18]  Chein-Wei Jen,et al.  A low power and memory efficient distributed arithmetic design and its DCT application , 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

[19]  Jacob A. Abraham,et al.  Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing , 1988, ICPP.

[20]  Peter Pirsch,et al.  A fault-tolerant DCT-architecture based on distributed arithmetic , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[21]  Hee Yong Youn,et al.  On concurrent error detection, location, and correction of FFT networks , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

[22]  Hee Yong Youn,et al.  An Efficient Algorithm-Based Concurrent Error Detection for FFT Networks , 1995, IEEE Trans. Computers.

[23]  Michael N. Lovellette,et al.  Strategies for fault-tolerant, space-based computing: Lessons learned from the ARGOS testbed , 2002, Proceedings, IEEE Aerospace Conference.

[24]  Peter Hazucha,et al.  Characterization of soft errors caused by single event upsets in CMOS processes , 2004, IEEE Transactions on Dependable and Secure Computing.

[25]  N. Ahmed,et al.  Discrete Cosine Transform , 1996 .

[26]  M.N.S. Swamy,et al.  Effects of errors and error recovery in images compressed by the JPEG still image compression standard algorithm , 1994, 1994 Proceedings of Canadian Conference on Electrical and Computer Engineering.

[27]  Earl E. Swartzlander,et al.  DCT Implementation with Distributed Arithmetic , 2001, IEEE Trans. Computers.