The efficient implementation of multimedia algorithms, for the ever increasing complexity of the specifications and the emergence of the new generation of processing platforms characterized by multicore and multicomponent parallel architectures, requires appropriate design space exploration procedures as preliminary step for any implementation. This paper describes a new platform aiming at supporting the algorithm and architecture co-exploration starting by a pure software specification that is gradually transformed into a possibly mixed SW and HW implementation. The process is based on profiling capabilities supported by the new platform specifically conceived to study and optimize data flows and data transfers between SW and HW modules. Different explicit or implicit (i.e. virtual memory extensions) data transfer modes can be profiled in the co-exploration process, by using minimal SW reconfiguration, thus minimizing any SW/HW re-writing effort in the co-exploration stage. Such optimization capabilities can be used to achieve different optimization objectives such as the optimization of memory architectures or low power designs by appropriate minimization of data transfers. Experimental results and an example of the usage of the platform are provided for the design case of a motion estimation module for video encoding.
[1]
Christophe Lucarz,et al.
A HW/SW codesign platform for Algorithm-Architecture mapping
,
2007
.
[2]
Marco Mattavelli,et al.
Configurable motion-estimation hardware accelerator module for the MPEG-4 reference hardware description platform
,
2005,
IEEE International Conference on Image Processing 2005.
[3]
Marco Mattavelli,et al.
A Virtual Socket Framework for Rapid Emulation of Video and Multimedia Designs
,
2005,
2005 IEEE International Conference on Multimedia and Expo.
[4]
Christophe Lucarz,et al.
Reconfigurable Media Coding: A New Specification Model for Multimedia Coders
,
2007,
2007 IEEE Workshop on Signal Processing Systems.
[5]
T.S. Mohamed,et al.
Integrated hardware-software platform for image processing applications
,
2004,
4th IEEE International Workshop on System-on-Chip for Real-Time Applications.
[6]
Choudhury A. Rahman,et al.
A hardware-accelerated framework with IP-blocks for application in MPEG-4
,
2005,
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05).