Fixed bit width precision multiplier having low energy properties
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Technical Field The present invention relates to integrated circuits, and particularly relates to a high-precision low-power fixed bit width of the multiplier. Precision fixed bit width of the multiplier according to the present invention, comprises a coding circuit CSD, high partial product generating circuit, a compensation circuit and a low partial product compression circuit, the external input data input end of the CSD encoding circuit, which output end the upper portion low product generating circuit and a compensation circuit; said upper partial product generating circuit connected to the external input data, an output portion terminating product compression circuit; compensation circuit connected to said low external input data, an output portion terminating product compressor circuit; the partial product outputs the compressed data circuit terminating external output. Advantageous effects of the present invention is to achieve a fixed bit width CSD multiplier having low power consumption and a higher speed, to achieve a high accuracy, low energy consumption and practical Multiplier fixed bit width. In particular, the present invention is applicable to low-power Multiply fixed bit wide precision.