Logic-enhanced memories for data-intensive processing

Emerging computer applications have unique high-volume data processing and high-performance requirements (e.g. multimedia systems). These requirements are not supported well by standard computer hardware: the major performance degrading factor being the limited memory bandwidth available. To alleviate this problem, we aim to assess and develop the utility of hardware memory enhanced with selected programmable processing capabilities as an alternative to the standard approaches. The key idea is to off-load simple, high-volume data processing to the memory itself in order to reduce the traffic between the processor and the memory units. We consider a simple mathematical model for logic-enhanced memory architectures, and using it, we exhibit the potential gains in performance.