Implementation and Performance Evaluation of a Fast Dynamic Control Scheme for Capacitor-Supported Interline DVR

The implementation of a fast dynamic control scheme for capacitor-supported interline dynamic voltage restorer (DVR) is presented in this paper. The power stage of the DVR consists of three inverters sharing the same dc link via a capacitor bank. Each inverter has an individual inner control loop for generating the gate signals for the switches. The inner loop is formed by a boundary controller with second-order switching surface, which can make the load voltage ideally revert to the steady state in two switching actions after supply voltage sags, and also gives output of low harmonic distortion. The load-voltage phase reference is common to all three inner loops and is generated by an outer control loop for regulating the dc-link capacitor voltage. Such structure can make the unsagged phase(s) and the dc-link capacitor to restore the sagged phase(s). Based on the steady-state and small-signal characteristics of the control loops, a set of design procedures will be provided. A 1.5-kVA, 220-V, 50-Hz prototype has been built and tested. The dynamic behaviors of the prototype under different sagged and swelled conditions and depths will be investigated. The quality of the load voltage under unbalanced and distorted phase voltages, and nonlinear inductive loads will be studied.

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