New Prefetch Technique Design for L2 Cache

The memory system remains a major performance bottleneck in the modern and future architectures. Cache unit design and optimization have become an increasingly important factor in determining the overall system performance. This dissertation focuses on the research of the prefetching technique of L2 Cache. A new prefetch technique (timing stride prefetching, TSP), which is suitable for prefetching at the L2 cache, is proposed. Compared with traditional stride prefetch technique, the TSP's timeliness is improved and its IPC (instructions per cycle) is increased by 8.3%