EBIST: a novel test generator with built-in fault detection capability

A novel design methodology for test pattern generation in BIST is presented. Here, faults and errors in the generator itself are detected. Two different design methodologies are presented. The first one guarantees all single fault/error detection and the second methodology is capable of detecting multiple faults and errors. Furthermore the proposed LFSRs do not have additional hardware overhead. Also, importantly, the test patterns generated have the potential to achieve superior fault coverage.

[1]  Dhiraj K. Pradhan,et al.  Fault-tolerant computing : theory and techniques , 1986 .

[2]  Dhiraj K. Pradhan,et al.  Store Address Generator with On-Line Fault-Detection Capability , 1977, IEEE Transactions on Computers.

[3]  Edward J. McCluskey,et al.  Circuits for pseudoexhaustive test pattern generation , 1986, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Sandeep K. Gupta,et al.  A methodology to design efficient BIST test pattern generators , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[5]  Shu Lin,et al.  Error control coding : fundamentals and applications , 1983 .

[6]  Janusz Rajski,et al.  Logic BIST for large industrial designs: real issues and case studies , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[7]  Nur A. Touba,et al.  Reducing test data volume using external/LBIST hybrid test patterns , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[8]  N. S. Vasanthavada.  Group parity prediction scheme for concurrent testing of linear feedback shift registers , 1985 .

[9]  John A. Waicukauski,et al.  Fault detection effectiveness of weighted random patterns , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[10]  Dhiraj K. Pradhan,et al.  SHIFT REGISTERS DESIGNED FOR ON-LINE FAULT DETECTION , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

[11]  Dhiraj K. Pradhan,et al.  A BIST Pattern Generator Design for Near-Perfect Fault Coverage , 2003, IEEE Trans. Computers.

[12]  Niraj K. Jha,et al.  Testing of Digital Systems , 2003 .

[13]  Dhiraj K. Pradhan,et al.  A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression , 1991, IEEE Trans. Computers.

[14]  Dhiraj K. Pradhan,et al.  GLFSR-a new test pattern generator for built-in-self-test , 1994, Proceedings., International Test Conference.