Measurement and simulation of stacked die thermal resistances

Packages with multiple die provide additional challenges when documenting their thermal performance. To explore the thermal performance of multi-chip packages, stacked die configurations were chosen with the die stacked upon each other. A plastic ball grid array package (PBGA) was thermally tested with three die configurations. The thermal performance of the package was determined using the JEDEC 51 specifications. The package was also simulated using a finite element simulation to better illustrate the package performance. In addition, the validity of the superposition technique was evaluated in the determination of junction temperatures with change in power of the various die

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